1. Field of the Invention
This invention relates generally to switching DC-DC regulators, and more particularly, to switching DC-DC regulators that maintain high light load efficiency at a fixed switching frequency when using large external FET switching devices.
2. Description of the Prior Art
Switching DC-DC regulators having large output FET devices capable of switching synchronously at high frequencies (greater than 680 kHz) and at light loading are well known. These known devices use any one or more known techniques in their attempts to attain higher light load efficiency. These techniques, however, rely on methods that are not always possible to implement, or otherwise do not meet the needs of integrated circuit applications such as integrated circuits defined by cellular phone specifications. A significant problem associated with light loading is that more power is lost in turning a large FET switch on and off, than that lost due to the resistance of the switch itself.
Basic variables associated with power loss relating to switching DC-DC regulators are seen in the well known power loss equation (1) below:
Ploss=2Cg*Vgs2*fs+RdsON*I2/3Tsxe2x80x83xe2x80x83(1)
where fs is the switching frequency, RdsON is the switch on resistance, Cg is the gate capacitance, Vgs is the gate switching voltage, I is the current through a switching device, and Ts is the switching period. At light loads, the switching frequency fs term dominates, so presently known techniques seek to minimize it. U.S. Pat. No. 5,912,552, entitled DC to DC Converter With High Efficiency for Light Loads, issued Jun. 15, 1999 to Tateishi, discloses use of a burst mode that reduces fs by passing more energy each time and that randomly turns on when needed. This technique is useful only in cases that can tolerate high ripple and broad spectrum noise. This technique is not, however, acceptable in many RF applications. U.S. Pat. No. 5,731,731, entitled High Efficiency Switching Regulator with Adaptive Drive Output Circuit, issued Mar. 24, 1998 to Wilcox, et al., discloses reduction of Cg with a smaller switch during light loading conditions. This technique is a good strategy when the output FET devices are integrated into the IC. This technique, however, is very costly in parts count, PCB area and pin count when the output FET devices are external to the IC. This technique is however, unacceptable for certain integrated circuit applications such as compact, cost sensitive cell phone applications. U.S. Pat. No. 5,420,777, entitled Switching Type. DC-DC Converter Having Increasing Conversion Efficiency At Light Load, issued May 30, 1995 to Muto, disclosing a technique for reducing Vgs. This technique, however, applies only to nonsynchronous boost applications. Further, the technique of Muto is not feasible at high switching frequencies since a comparator can not act fast enough, given the current state of processing technology. Moto does not disclose or suggest a method or structure for limiting the P-side FET gate voltage to Vddxe2x88x92Vgs, which is necessary to accommodate a synchronous switcher topology. High power and current switching regulator ICs, such as those described herein above, often have efficiencies below 30% at low current loads.
In view of the foregoing, a need exists for a switching regulator technique capable of maintaining high light load efficiency at a fixed high switching frequency f, when using large external FET devices.
The present invention is directed to a switching regulator capable of maintaining high light load efficiency at a fixed switching frequency fs, even when using large external FET devices. The switch node (SWn) is used as a control reference for the Vgs gate drive limiting; and the appropriate on-time gate drive FET as the controlled switch. The switch node (SWn) precisely times the Vgs setting process and provides substantially all of the energy necessary to turn on the main FET devices. The drive signals are like those for a typical switching regulator. The output driver FET, PonSW, that turns on the main PMOS device, and the output driver FET, NonSW, that turns on the main NMOS device, however, each have their source referenced to the switch node (SWn) instead of Vdd or ground respectively.
In one aspect of the present invention, a MOS-based switch mode power converter has the gate drive of the output FET devices configured such that the on-time driver FET device has its source connected to the output switch node.
In another aspect of the present invention, a switching regulator detection circuit is provided that senses the output switch node voltage to determine light load conditions.
In still another aspect of the present invention, a switching regulator voltage setting circuit is provided to drive the gate switching voltage Vgs of the output FET device to a predetermined minimal value that guarantees FET turn-on and generates a signal to end the Vgs setting process.
In yet another aspect of the present invention, a switching regulator technique is provided whereby the on-time driver FET device recirculates substantially all the gate drive energy necessary by reusing normally wasted inductor energy.
In another aspect of the present invention, a MOS-based switch mode power converter is provided to establish exact timing parameters necessary to turn off the gate drive of the out FET devices.
In still another aspect of the present invention, a switching regulator is provided that automatically clamps the output FET device switch node in discontinuous mode to limit ringing to one Vt above Vdd or below ground when all output FET devices are off.
In yet another aspect of the present invention, a switching regulator is provided that guarantees a minimum gate drive speed during normal load conditions as determined by a light load detection circuit.
In still another aspect of the present invention, a switching regulator is provided that guarantees the output FET device turns on during light loading conditions as determined by a light load detection circuit.
In another aspect of the present invention, a switching regulator is provided whereby a multiplicity of gate drive devices operate to assist the on-time driver FET device to quickly turn on the output FET device, thereby preserving die area.